DSPIC33FJ64GP310AT-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ64GP310AT-I/PF

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJXXXGPX06/X08/X10

FIGURE 8-1:

SRAM

TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS

DMA Controller

Peripheral Indirect Address

DMA RAM

PORT 1 PORT 2

DMA

Channels

DMA

Ready

Peripheral 3

CPU DMA

SRAM X-Bus

DMA DS Bus

CPU Peripheral DS Bus

CPU

Non-DMA

Ready

Peripheral

Note: CPU and DMA address buses are not shown for clarity.

8.1 DMAC Registers

Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)

contains the following registers:

• A 16-bit DMA Channel Control register

(DMAxCON)

• A 16-bit DMA Channel IRQ Select register

(DMAxREQ)

• A 16-bit DMA RAM Primary Start Address Offset

register (DMAxSTA)

• A 16-bit DMA RAM Secondary Start Address

Offset register (DMAxSTB)

• A 16-bit DMA Peripheral Address register

(DMAxPAD)

• A 10-bit DMA Transfer Count register (DMAxCNT)

An additional pair of status registers, DMACS0 and

DMACS1, are common to all DMAC channels.

CPU DMA

DMA

Ready

Peripheral 1

CPU DMA

DMA

Ready

Peripheral 2

DS70286C-page 128

© 2009 Microchip Technology Inc.

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