DSPIC33FJ64GP310AT-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ64GP310AT-I/PF

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJXXXGPX06/X08/X10

22.0 SPECIAL FEATURES

Note:

This data sheet summarizes the features

of the dsPIC33FJXXXGPX06/X08/X10

family of devices. However, it is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to Section 23.

“CodeGuard™ Security” (DS70199),

Section 24. “Programming and

Diagnostics” (DS70207), and Section

25. “Device Configuration” (DS70194)

in the “dsPIC33F Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

dsPIC33FJXXXGPX06/X08/X10 devices include

several features intended to maximize application

flexibility and reliability, and minimize cost through elim-

ination of external components. These are:

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection and CodeGuard™ Security

• JTAG Boundary Scan Interface

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Emulation

22.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’), to select

various device configurations. These bits are mapped

starting at program memory location 0xF80000.

The device Configuration register map is shown in

Table 22-1.

The individual Configuration bit descriptions for the

FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and

FICD Configuration registers are shown in Table 22-2.

Note that address 0xF80000 is beyond the user program

memory space. In fact, it belongs to the configuration

memory space (0x800000-0xFFFFFF) which can only be

accessed using table reads and table writes.

The upper byte of all device Configuration registers

should always be ‘1111 1111’. This makes them

appear to be NOP instructions in the remote event that

their locations are ever executed by accident. Since

Configuration bits are not implemented in the

corresponding locations, writing ‘1’s to these locations

has no effect on device operation.

To prevent inadvertent configuration changes during

code execution, all programmable Configuration bits

are write-once. After a bit is initially programmed during

a power cycle, it cannot be written to again. Changing

a device configuration requires that power to the device

be cycled.

TABLE 22-1: DEVICE CONFIGURATION REGISTER MAP

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

0xF80000 FBS

RBS<1:0>

—

—

BSS<2:0>

BWRP

0xF80002 FSS

RSS<1:0>

—

—

SSS<2:0>

SWRP

0xF80004 FGS

—

—

—

0xF80006 FOSCSEL IESO Reserved(2)

—

—

—

GSS1 GSS0 GWRP

—

—

FNOSC<2:0>

0xF80008 FOSC

FCKSM<1:0>

—

—

— OSCIOFNC POSCMD<1:0>

0xF8000A FWDT

FWDTEN WINDIS

—

WDTPRE

WDTPOST<3:0>

0xF8000C FPOR

0xF8000E FICD

—

—

—

—

—

Reserved(1)

JTAGEN

—

—

FPWRT<2:0>

—

ICS<1:0>

0xF80010 FUID0

User Unit ID Byte 0

0xF80012 FUID1

User Unit ID Byte 1

0xF80014 FUID2

User Unit ID Byte 2

0xF80016 FUID3

User Unit ID Byte 3

Note 1: When read, these bits will appear as ‘1’. When you write to these bits, set these bits to ‘1’.

2: When read, this bit returns the current programmed value.

© 2009 Microchip Technology Inc.

DS70286C-page 237

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