dsPIC33FJXXXGPX06A/X08A/X10A
9.0 OSCILLATOR
CONFIGURATION
Note 1: This data sheet summarizes the
features of the dsPIC33FJXXXGPX06A/
X08A/X10A family of devices. However,
it is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 7. “Oscillator”
(DS70186) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33FJXXXGPX06A/X08A/X10A oscillator
system provides:
• Various external and internal oscillator options as
clock sources
• An on-chip PLL to scale the internal operating
frequency to the required system clock frequency
• The internal FRC oscillator can also be used with
the PLL, thereby allowing full-speed operation
without any external clock generation hardware
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• An Oscillator Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection
A simplified diagram of the oscillator system is shown
in Figure 9-1.
FIGURE 9-1:
dsPIC33FJXXXGPX06A/X08A/X10A OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator
OSC1
R(2)
S3
OSC2
S1
POSCMD<1:0>
PLL(1)
XT, HS, EC
S2
XTPLL, HSPLL,
ECPLL, FRCPLL
S1/S3
DOZE<2:0>
FCY
FP(3)
FRC
Oscillator
FRCDIVN S7
÷2
FOSC
TUN<5:0>
FRCDIV<2:0>
÷ 16
SOSCO
SOSCI
LPRC
Oscillator
Secondary Oscillator
LPOSCEN
FRCDIV16 S6
FRC S0
LPRC
S5
SOSC
S4
Clock Fail Clock Switch Reset
S7
NOSC<2:0> FNOSC<2:0>
WDT, PWRT,
FSCM
Timer 1
Note 1:
2:
3:
See Figure 9-2 for PLL details.
If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 MΩ must be connected.
The term, FP refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU.
Throughout this document FP and FCY are used interchangeably, except in the case of Doze mode. FP and FCY will be
different when Doze mode is used in any ratio other than 1:1, which is the default.
© 2011 Microchip Technology Inc.
DS70593C-page 149