DSPIC33FJ64GP706AE/PF View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ64GP706AE/PF Datasheet PDF : 350 Pages
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dsPIC33FJXXXGPX06A/X08A/X10A
16.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGPX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the infor-
mation in this data sheet, refer to Section
18. “Serial Peripheral Interface (SPI)”
(DS70206) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift
registers, display drivers, Analog-to-Digital Converters
(ADC), etc. The SPI module is compatible with SPI and
SIOP from Motorola®.
Note:
In this section, the SPI modules are
referred to together as SPIx, or
separately as SPI1 and SPI2. Special
Function Registers will follow a similar
notation. For example, SPIxCON refers to
the control register for the SPI1 or SPI2
module.
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates various status conditions.
The serial interface consists of 4 pins: SDIx (serial data
input), SDOx (serial data output), SCKx (shift clock input
or output), and SSx (active-low slave select).
In Master mode operation, SCK is a clock output but in
Slave mode, it is a clock input.
FIGURE 16-1:
SCKx
SPI MODULE BLOCK DIAGRAM
SSx
SDOx
SDIx
Sync
Control
Control
Clock
Select
Edge
Shift Control
bit 0
SPIxSR
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary FCY
Prescaler
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
Transfer
Transfer
SPIxRXB SPIxTXB
SPIxBUF
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
© 2011 Microchip Technology Inc.
DS70593C-page 183
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