DSPIC33FJ64GP706AI/PF View Datasheet(PDF) - Microchip Technology
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DSPIC33FJ64GP706AI/PF Datasheet PDF : 350 Pages
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dsPIC33FJXXXGPX06A/X08A/X10A
22.2 On-Chip Voltage Regulator
All of the dsPIC33FJXXXGPX06A/X08A/X10A devices
power their core digital logic at a nominal 2.5V. This
may create an issue for designs that are required to
operate at a higher typical voltage, such as 3.3V. To
simplify system design, all devices in the
dsPIC33FJXXXGPX06A/X08A/X10A family incor-
porate an on-chip regulator that allows the device to
run its core logic from VDD.
The regulator provides power to the core from the
other VDD pins. The regulator requires that a
low-ESR (less than 5 ohms) capacitor (such as
tantalum or ceramic) be connected to the VCAP pin
(Figure 22-1). This helps to maintain the stability of
the regulator. The recommended value for the filter
capacitor is provided in Table 25-13 of Section 25.0
“Electrical Characteristics”.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
On a POR, it takes approximately 20 μs for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
FIGURE 22-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1)
3.3V
dsPIC33F
CEFC
VDD
VCAP
VSS
22.3 BOR: Brown-out Reset
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit that monitors the
regulated voltage VCAP. The main purpose of the BOR
module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines or voltage sags due to
excessive current draw when a large inductive load is
turned on).
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>). Furthermore, if an oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) will be
applied before the internal Reset is released. If
TPWRT = 0 and a crystal oscillator is being used, then
a nominal delay of TFSCM = 100 is applied. The total
delay in this case is TFSCM.
The BOR Status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and will reset the
device should VDD fall below the BOR threshold
voltage.
Note 1:
2:
These are typical operating voltages. Refer to
Table 25-13 located in Section 25.1 “DC
Characteristics” for the full operating ranges
of VDD and VCAP.
It is important for the low-ESR capacitor to be
placed as close as possible to the VCAP pin.
DS70593C-page 256
© 2011 Microchip Technology Inc.
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