DSPIC33FJ64GP206AI/PF-ES View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ64GP206AI/PF-ES

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJXXXGPX06A/X08A/X10A

Revision C (March 2011)

This revision includes typographical and formatting

changes throughout the data sheet text. In addition, all

instances of VDDCORE have been removed.

All other major changes are referenced by their

respective section in the following table.

TABLE B-2: MAJOR SECTION UPDATES

Section Name

Update Description

Section 2.0 “Guidelines for Getting Started Updated the title of Section 2.3 “CPU Logic Filter Capacitor

with 16-Bit Digital Signal Controllers”

Connection (Vcap)”.

The frequency limitation for device PLL start-up conditions was

updated in Section 2.7 “Oscillator Value Conditions on Device

Start-up”.

Section 4.0 “Memory Organization”

Section 9.0 “Oscillator Configuration”

The second paragraph in Section 2.9 “Unused I/Os” was updated.

The All Resets values for the following SFRs in the Timer Register

Map were changed (see Table 4-6):

• TMR1

• TMR2

• TMR3

• TMR4

• TMR5

• TMR6

• TMR7

• TMR8

• TMR9

Added Note 3 to the OSCCON: Oscillator Control Register (see

Register 9-1).

Added Note 2 to the CLKDIV: Clock Divisor Register (see

Register 9-2).

Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see

Register 9-3).

Section 21.0 “10-Bit/12-Bit

Analog-to-Digital Converter (ADC)”

Section 22.0 “Special Features”

Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see

Register 9-4).

Updated the VREFL references in the ADC1 module block diagram

(see Figure 21-1).

Added a new paragraph and removed the third paragraph in

Section 22.1 “Configuration Bits”.

Added the column “RTSP Effects” to the Configuration Bits

Descriptions (see Table 22-2).

© 2011 Microchip Technology Inc.

DS70593C-page 341

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