DSPIC33FJ128GP310AI/MR View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ128GP310AI/MR

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

TABLE 4-31: PORTG REGISTER MAP(1)

File Name Addr Bit 15

Bit 14

Bit 13

Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

TRISG

PORTG

LATG

ODCG

Legend:

Note 1:

02E4 TRISG15 TRISG14 TRISG13 TRISG12

—

—

TRISG9 TRISG8 TRISG7 TRISG6

—

02E6 RG15

RG14

RG13

RG12

—

—

RG9

RG8

RG7

RG6

—

02E8 LATG15 LATG14 LATG13 LATG12

—

—

LATG9 LATG8 LATG7 LATG6

—

06E4 ODCG15 ODCG14 ODCG13 ODCG12

—

—

ODCG9 ODCG8 ODCG7 ODCG6

—

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.

The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

Bit 4

—

—

—

—

Bit 3

TRISG3

RG3

LATG3

ODCG3

Bit 2

TRISG2

RG2

LATG2

ODCG2

Bit 1

TRISG1

RG1

LATG1

ODCG1

Bit 0

TRISG0

RG0

LATG0

ODCG0

All

Resets

F3CF

xxxx

xxxx

0000

TABLE 4-32: SYSTEM CONTROL REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

RCON

OSCCON

CLKDIV

PLLFBD

OSCTUN

Legend:

Note 1:

2:

0740 TRAPR IOPUWR —

—

—

—

—

VREGS EXTR

SWR

0742

—

COSC<2:0>

—

NOSC<2:0>

CLKLOCK —

0744

ROI

DOZE<2:0>

DOZEN

FRCDIV<2:0>

PLLPOST<1:0>

0746

—

—

—

—

—

—

—

0748

—

—

—

—

—

—

—

—

—

—

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

RCON register Reset values dependent on type of Reset.

OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

SWDTEN WDTO SLEEP IDLE

BOR

LOCK

—

CF

— LPOSCEN

—

PLLPRE<4:0>

PLLDIV<8:0>

TUN<5:0>

POR

OSWEN

xxxx(1)

0300(2)

3040

0030

0000

TABLE 4-33: NVM REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

NVMCON

NVMKEY

Legend:

Note 1:

0760

WR

WREN WRERR

—

—

—

—

—

—

ERASE

—

—

0766

—

—

—

—

—

—

—

—

NVMKEY<7:0>

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.

Bit 2

Bit 1

NVMOP<3:0>

Bit 0

All

Resets

0000(1)

0000

TABLE 4-34: PMD REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10

Bit 9

Bit 8

Bit 7

PMD1

PMD2

PMD3

Legend:

0770 T5MD T4MD T3MD T2MD T1MD

—

—

DCIMD I2C1MD

0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD

0774 T9MD T8MD T7MD T6MD

—

—

—

—

—

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 6

U2MD

OC7MD

—

Bit 5

U1MD

OC6MD

—

Bit 4

Bit 3

Bit 2

SPI2MD

OC5MD

—

SPI1MD

OC4MD

—

C2MD

OC3MD

—

Bit 1

C1MD

OC2MD

I2C2MD

Bit 0

All

Resets

AD1MD

OC1MD

AD2MD

0000

0000

0000

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