dsPIC33FJXXXGPX06A/X08A/X10A
REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 0
POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1:
2:
3:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
For dsPIC33FJ256GPX06A/X08A/X10A devices, this bit is unimplemented and reads back programmed
value.
© 2011 Microchip Technology Inc.
DS70593C-page 89