TABLE 4-7: OUTPUT COMPARE REGISTER MAP
SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
—
—
OCSIDL
—
—
—
—
—
—
—
—
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
—
— OCSIDL —
—
—
—
—
—
—
—
OC3RS
018C
Output Compare 3 Secondary Register
OC3R
018E
Output Compare 3 Register
OC3CON
0190
—
— OCSIDL —
—
—
—
—
—
—
—
OC4RS
0192
Output Compare 4 Secondary Register
OC4R
0194
Output Compare 4 Register
OC4CON
0196
—
— OCSIDL —
—
—
—
—
—
—
—
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OCFLT OCTSEL
OCFLT OCTSEL
OCFLT OCTSEL
OCFLT OCTSEL
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
All
Resets
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP
SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1TCON
01C0 PTEN
—
PTSIDL
—
—
—
—
—
PTOPS<3:0>
P1TMR
01C2 PTDIR
PWM Timer Count Value Register
P1TPER
01C4
—
PWM Time Base Period Register
P1SECMP
01C6 SEVTDIR
PWM Special Event Compare Register
PWM1CON1 01C8
—
—
—
—
—
PMOD3 PMOD2 PMOD1
—
PEN3H PEN2H PEN1H
PWM1CON2 01CA
—
—
—
—
SEVOPS<3:0>
—
—
—
—
P1DTCON1 01CC
DTBPS<1:0>
DTB<5:0>
DTAPS<1:0>
P1DTCON2 01CE
—
—
—
—
—
—
—
—
—
—
DTS3A DTS3I
P1FLTACON 01D0
—
— FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM
—
—
—
P1OVDCON 01D4
—
— POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L
—
— POUT3H POUT3L
P1DC1
01D6
PWM Duty Cycle 1 Register
P1DC2
01D8
PWM Duty Cycle 2 Register
P1DC3
01DA
PWM Duty Cycle 3 Register
Legend: u = uninitialized bit, — = unimplemented, read as ‘0’
PTCKPS<1:0>
—
PEN3L
—
IUE
DTA<5:0>
DTS2A DTS2I
—
FAEN3
POUT2H POUT2L
PTMOD<1:0>
PEN2L
OSYNC
PEN1L
UDIS
DTS1A
FAEN2
POUT1H
DTS1I
FAEN1
POUT1L
Reset
State
0000
0000
0000
0000
00FF
0000
0000
0000
0000
FF00
0000
0000
0000