DSPIC33FJ128MC202-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ128MC202-I/SP

16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Motor Control PWM and Advanced Analog

Microchip Technology 

TABLE 4-9: 2-OUTPUT PWM2 REGISTER MAP

SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

P2TCON

05C0 PTEN

—

PTSIDL

—

P2TMR

05C2 PTDIR

P2TPER

05C4

—

P2SECMP

05C6 SEVTDIR

PWM2CON1 05C8

—

—

—

—

PWM2CON2 05CA

—

—

—

—

P2DTCON1 05CC

DTBPS<1:0>

P2DTCON2 05CE

—

—

—

—

P2FLTACON 05D0

—

—

—

—

P2OVDCON 05D4

—

—

—

—

P2DC1

05D6

Legend: — = unimplemented, read as ‘0’

—

—

—

—

PTOPS<3:0>

PWM Timer Count Value Register

PWM Time Base Period Register

PWM Special Event Compare Register

—

—

—

PMOD1

—

—

—

SEVOPS<3:0>

—

—

—

DTB<5:0>

DTAPS<1:0>

—

—

—

—

—

—

—

—

— FAOV1H FAOV1L FLTAM

—

—

—

— POVD1H POVD1L —

—

—

PWM Duty Cycle #1 Register

Bit 4

PEN1H

—

—

—

—

Bit 3

Bit 2

PTCKPS<1:0>

—

—

—

IUE

DTA<5:0>

—

—

—

—

—

—

Bit 1

Bit 0 Reset State

PTMOD<1:0>

—

PEN1L

OSYNC UDIS

DTS1A DTS1I

—

FAEN1

POUT1H POUT1L

0000

0000

0000

0000

00FF

0000

0000

0000

0000

FF00

0000

TABLE 4-10: QEI1 REGISTER MAP

SFR

Name

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7

Bit 6

Bit 5

QEI1CON

01E0 CNTERR

—

DFLT1CON 01E2

—

—

POS1CNT 01E4

MAX1CNT 01E6

Legend: — = unimplemented, read as ‘0’

QEISIDL INDX UPDN

—

—

—

QEIM<2:0>

SWPAB PCDOUT TQGATE

IMV<1:0> CEID QEOUT

QECK<2:0>

Position Counter<15:0>

Maximum Count<15:0>

Bit 4

Bit 3

TQCKPS<1:0>

—

Bit 2 Bit 1

Bit 0

Reset State

POSRES TQCS UPDN_SRC

—

—

—

0000

0000

0000

FFFF

TABLE 4-11: QEI2 REGISTER MAP

SFR

Name

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7

Bit 6

Bit 5

QEI2CON

01F0 CNTERR

—

DFLT2CON 01F2

—

—

POS2CNT 01F4

MAX2CNT 01F6

Legend: — = unimplemented, read as ‘0’

QEISIDL INDX UPDN

—

—

—

QEIM<2:0>

SWPAB PCDOUT TQGATE

IMV<1:0> CEID QEOUT

QECK<2:0>

Position Counter<15:0>

Maximum Count<15:0>

Bit 4

Bit 3

TQCKPS<1:0>

—

Bit 2

Bit 1

Bit 0

Reset State

POSRES TQCS UPDN_SRC

—

—

—

0000

0000

0000

FFFF

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