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STM32F373VC(2013) View Datasheet(PDF) - STMicroelectronics

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STM32F373VC Datasheet PDF : 131 Pages
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STM32F37xxx
Electrical characteristics
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 58 for SPI or in Table 59 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 22.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Symbol
Table 58. SPI characteristics
Parameter
Conditions
Min Max Unit
fSCK
1/tc(SCK)(1)
SPI clock frequency
Master mode
Slave mode
-
18
-
18
MHz
tr(SCK)
tf(SCK)(1)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
-
8
ns
DuCy(SCK)(1)
SPI slave input clock
duty cycle
Slave mode
30
70
%
tsu(NSS)(1)
th(NSS)(1)
tw(SCKH)(1)
tw(SCKL)(1)
NSS setup time
Slave mode
NSS hold time
Slave mode
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
2Tpclk -
4Tpclk -
Tpclk/2 Tpclk/2
-3
+3
tsu(MI) (1)
tsu(SI)(1)
Data input setup time
Master mode
Slave mode
5.5
-
6.5
-
th(MI) (1)
Data input hold time
Master mode
5
th(SI)(1)
Slave mode
5
ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 24 MHz
0
tdis(SO)(1)(3) Data output disable time Slave mode
0
tv(SO) (1) Data output valid time Slave mode (after enable edge)
-
tv(MO)(1) Data output valid time Master mode (after enable edge) -
th(SO)(1)
th(MO)(1)
Data output hold time
Slave mode (after enable edge) 15
Master mode (after enable edge) 4
-
-
ns
4Tpclk
24
39
3
-
-
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z.
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