STM32F302CBY7TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F302CBY7TR

ARM®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+ 40KB SRAM, 2 ADCs, 1 DAC ch., 4 comp, 2 PGA, timers, 2.0-3.6 V

STMicroelectronics 

STM32F302xB STM32F302xC

Functional overview

Table 4. STM32F302xB/STM32F302xC peripheral interconnect matrix (continued)

Interconnect source

Interconnect

destination

Interconnect action

GPIO

RTCCLK

HSE/32

MC0

CSS

CPU (hard fault)

COMPx

PVD

GPIO

TIM16

TIM1,

TIM15, 16, 17

Clock source used as input channel for HSI and

LSI calibration

Timer break

GPIO

DAC1

TIMx

ADCx

DAC1

COMPx

External trigger, timer break

Conversion external trigger

Comparator inverting input

Note:

For more details about the interconnect actions, please refer to the corresponding sections

in the reference manual (RM0365.

3.9

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and

the low speed APB (APB1) domains. The maximum frequency of the AHB and the high

speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed

APB domain is 36 MHz.

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