R5F1036AASP-W0 View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

R5F1036AASP-W0

RENESAS MCU True Low Power Platform (as low as 63 μA/MHz), 1.8V to 5.5V operation, 2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications

Renesas Electronics 

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: TA = −40 to +105°C)

(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)

(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

Unit

MIN.

MAX.

SCKp cycle time Note4

tKCY2

4.0 V ≤ VDD ≤ 5.5 V

20 MHz < fMCK

16/fMCK

ns

fMCK ≤ 20 MHz

12/fMCK

ns

2.7 V ≤ VDD ≤ 5.5 V

16 MHz < fMCK

16/fMCK

ns

fMCK ≤ 16 MHz

12/fMCK

ns

2.4 V ≤ VDD ≤ 5.5 V

12/fMCK

ns

and 1000

SCKp high-/low-level width tKH2,

tKL2

SIp setup time (to SCKp↑) tSIK2

Note 1

SIp hold time

(from SCKp↑) Note 2

Delay time from SCKp↓ to

SOp output Note 3

tKSI2

tKSO2

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD ≤ 5.5 V

2.4 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD ≤ 5.5 V

2.4 V ≤ VDD ≤ 5.5 V

C = 30 pF Note4

2.7 V ≤ VDD ≤ 5.5 V

2.4 V ≤ VDD ≤ 5.5 V

tKCY2/2−14

tKCY2/2−16

tKCY2/2−36

1/fMCK + 40

1/fMCK + 60

1/fMCK + 62

ns

ns

ns

ns

ns

ns

2/fMCK + 66

ns

2/fMCK + 113

ns

Notes 1.

2.

3.

4.

5.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to

SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from

SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output

becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

C is the load capacitance of the SOp output lines.

Transfer rate in the SNOOZE mode: MAX. 1 Mbps

Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin

by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,

POM4).

CSI mode connection diagram (during communication at same potential)

SCKp

RL78

microcontroller

SIp

SOp

SCK

SO User's device

SI

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 79 of 106

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