Symbol
Parameter
Min
Typ
Max
Unit
fsclk
PCM clock frequency (Slave mode: input)
64
-
(a)
kHz
fsclk
PCM clock frequency (GCI mode)
128
-
(b)
kHz
tsclkl
PCM_CLK low time
200
-
-
ns
tsclkh
PCM_CLK high time
200
-
-
ns
thsclksynch
Hold time from PCM_CLK low to PCM_SYNC high
2
-
-
ns
013 tsusclksynch
Set-up time for PCM_SYNC high to PCM_CLK low
20
-
-
mber 27, 2 tdpout
Delay time from PCM_SYNC or PCM_CLK,
whichever is later, to valid PCM_OUT data (Long
-
Frame Sync only)
-
20
epte tdsclkhpout
Delay time from CLK high to PCM_OUT valid data
-
-
15
- Friday, S tdpoutz
Delay time from PCM_SYNC or PCM_CLK low,
whichever is later, to PCM_OUT data line high
-
impedance
-
15
om.cn tsupinsclkl
Set-up time for PCM_IN valid to CLK low
20
-
-
oint.c thpinsclkl
Hold time for PCM_CLK low to PCM_IN invalid
2
-
-
excelp Table 9.7: PCM Slave Timing
u - (a) Max frequency is the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK
ho (b) Max frequency is twice the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK
qingbo keven.z PCM_CLK
f
sclk
t
sclkh
t
tsclkl
Prepared for PCM_SYNC
t
hsclksynch
t
susclksynch
ns
ns
ns
ns
ns
ns
PCM_OUT
t
dpout
MSB (LSB)
t
dsclkhpout
t ,t
rf
LSB (MSB)
t
dpoutz
t
dpoutz
PCM_IN
t
supinsclkl
t
hpinsclkl
MSB (LSB)
LSB (MSB)
Figure 9.18: PCM Slave Timing Long Frame Sync
Production Information
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