DSPIC33FJ16GS204-I/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ16GS204-I/SP Datasheet PDF : 346 Pages
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 7-1:
R-0
OA
bit 15
SR: CPU STATUS REGISTER(1)
R-0
R/C-0
R/C-0
OB
SA
SB
R-0
OAB
R/W-0(3)
R/W-0(3)
R/W-0(3)
R-0
IPL2(2)
IPL1(2)
IPL0(2)
RA
bit 7
R/W-0
N
R/C-0
SAB
R/W-0
OV
R -0
DA
R/W-0
Z
R/W-0
DC
bit 8
R/W-0
C
bit 0
Legend:
C = Clearable bit
S = Settable bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1)
U-0
U-0
U-0
U-0
R/W-0
R-0
—
—
—
US
EDT
bit 15
R-0
DL<2:0>
R-0
bit 8
R/W-0
SATA
bit 7
R/W-0
SATB
R/W-1
SATDW
R/W-0
ACCSAT
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
Legend:
R = Readable bit
0’ = Bit is cleared
C = Clearable bit
W = Writable bit
‘x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS70318D-page 100
Preliminary
© 2009 Microchip Technology Inc.
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