dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 15
R/W-0
PSEMIE
U-0
—
bit 8
U-0
—
bit 7
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
bit 9
bit 8-0
Unimplemented: Read as ‘0’
PSEMIE: PWM Special Event Match Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
REGISTER 7-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
U-0
—
bit 7
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
—
—
—
—
—
U1EIE
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-2
bit 1
bit 0
Unimplemented: Read as ‘0’
U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
DS70318D-page 114
Preliminary
© 2009 Microchip Technology Inc.