dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 7-18: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
U-0
—
bit 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
ADCP6IE(3) ADCP5IE(1) ADCP4IE(1) ADCP3IE(2) ADCP2IE(3)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4
bit
bit
bit
bit
Unimplemented: Read as ‘0’
ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit(3)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
ADCP5IE: ADC Pair 5 Conversion Done Interrupt Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
ADCP4IE: ADC Pair 4 Conversion Done Interrupt Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit(2)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit(3)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Note 1: These bits are not implemented in dsPIC33FJ06GS101/102/202 and dsPIC33FJ16GS402/402/502
devices.
2: This bit is not implemented in dsPIC33FJ06GS102/202 devices.
3: This bit is not implemented in dsPIC33FJ06GS101 devices.
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 117