dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 7-30: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
—
AC2IP<2:0>(1)
—
—
—
bit 15
U-0
—
bit 8
U-0
—
bit 7
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11-01
Unimplemented: Read as ‘0’
AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits(1)
111 = Interrupt is priority 7 (highest priority)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Unimplemented: Read as ‘0’
Note 1: These bits are not implemented in dsPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices.
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 127