DSPIC33FJ16GS204-I/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ16GS204-I/SP Datasheet PDF : 346 Pages
| |||
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
8.1 CPU Clocking System
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices provide six system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with Postscaler
8.1.1 SYSTEM CLOCK SOURCES
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
The primary oscillator can use one of the following as
its clock source:
• XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
• HS (High-Speed Crystal): Crystals in the range of
10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
• EC (External Clock): The external clock signal is
directly applied to the OSC1 pin.
The LPRC internal oscIllator runs at a nominal
frequency of 32.768 kHz. It is also used as a reference
clock by the Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM).
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase-Locked Loop (PLL) to provide a wide range of
output frequencies for device operation. PLL
configuration is described in Section 8.1.3 “PLL Con-
figuration”.
The FRC frequency depends on the FRC accuracy
(see Table 24-20) and the value of the FRC Oscillator
Tuning register (see Register 8-4).
8.1.2 SYSTEM CLOCK SELECTION
The oscillator source used at a device Power-on Reset
event is selected using Configuration bit settings. The
oscillator Configuration bit settings are located in the
Configuration registers in the program memory. (Refer
to Section 21.1 “Configuration Bits” for further
details.) The Initial Oscillator Selection Configuration
bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary
Oscillator Mode Select Configuration bits,
POSCMD<1:0> (FOSC<1:0>), select the oscillator
source that is used at a Power-on Reset. The FRC
primary oscillator is the default (unprogrammed)
selection.
The Configuration bits allow users to choose among
12 different clock modes, shown in Table 8-1.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected), FOSC, is divided by 2
to generate the device instruction clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device and speeds up to 40
MHz are supported by the dsPIC33FJ06GS101/X02
and dsPIC33FJ16GSX02/X04 architecture.
Instruction execution speed or device operating
frequency, FCY, is given by Equation 8-1.
EQUATION 8-1: DEVICE OPERATING
FREQUENCY
FCY = FOSC/2
TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source POSCMD<1:0> FNOSC<2:0>
Fast RC Oscillator with Divide-by-N (FRCDIVN)
Internal
xx
111
Fast RC Oscillator with Divide-by-16 (FRCDIV16)
Internal
xx
110
Low-Power RC Oscillator (LPRC)
Internal
xx
101
Reserved
Reserved
xx
100
Primary Oscillator (HS) with PLL (HSPLL)
Primary
10
011
Primary Oscillator (XT) with PLL (XTPLL)
Primary
01
011
Primary Oscillator (EC) with PLL (ECPLL)
Primary
00
011
Primary Oscillator (HS)
Primary
10
010
Primary Oscillator (XT)
Primary
01
010
Primary Oscillator (EC)
Primary
00
010
Fast RC Oscillator with PLL (FRCPLL)
Internal
xx
001
Fast RC Oscillator (FRC)
Internal
xx
000
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
Note
1, 2
1
1
—
—
—
1
—
—
1
1
1
DS70318D-page 136
Preliminary
© 2009 Microchip Technology Inc.
Share Link: 