DSPIC33FJ06GS101-E/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ06GS101-E/SO Datasheet PDF : 346 Pages
| |||
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
11.0 TIMER1
Note:
This data sheet summarizes the features of
the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, Section 11. “Timers”
(DS70205), which is available from the
Microchip web site (www.microchip.com).
The Timer1 module is a 16-bit timer, which can serve
as a time counter for the Real-Time Clock (RTC), or
operate as a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be operated from the low-power 32 kHz
crystal oscillator available on the device
• Can be operated in Asynchronous Counter mode
from an external clock source.
• The external clock input (T1CK) can optionally be
synchronized to the internal device clock and the
clock synchronization is performed after the
prescaler.
The unique features of Timer1 allow it to be used for
Real-Time Clock (RTC) applications. A block diagram
of Timer1 is shown in Figure 11-1.
The Timer1 module can operate in one of the following
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit (TCS): T1CON<1>
• Timer Synchronization Control bit (TSYNC):
T1CON<2>
• Timer Gate Control bit (TGATE): T1CON<6>
The timer control bit settings for different operating
modes are given in the Table 11-1.
TABLE 11-1: TIMER MODE SETTINGS
Mode
TCS
TGATE TSYNC
Timer
0
0
x
Gated Timer
0
1
x
Synchronous
1
x
1
Counter
Asynchronous
1
x
0
Counter
FIGURE 11-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
T1CK
Gate
Sync
Falling Edge
Detect
FCY Prescaler
10
(/n)
TCKPS<1:0>
00
1
Prescaler
(/n)
x1
Sync
0
TCKPS<1:0>
TSYNC
TGATE
TCS
1
Set T1IF Flag
0
TMR1
Reset TGATE
Equal
Comparator
PR1
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 183
Share Link: 