DSPIC33FJ06GS502-I/ML View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ06GS502-I/ML Datasheet PDF : 346 Pages
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
FIGURE 6-2:
SYSTEM RESET TIMING
VPOR
VBOR
VDD
1
POR Reset
TPOR
TBOR
2
BOR Reset
SYSRST
3
TPWRT
4
Oscillator Clock
FSCM
Device Status
TOSCD
TOST
Reset
TLOCK
6
TFSCM
5
Run
Time
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed.
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses
the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output
becomes stable.
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period
of time (TPWRT) after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the
appropriate level for full-speed operation. After the delay, TPWRT has elapsed and the SYSRST becomes
inactive, which in turn, enables the selected oscillator to start generating clock cycles.
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in
Table 6-1. Refer to Section 8.0 “Oscillator Configuration” for more information.
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application
programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up
routine.
6: If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is
ready and the delay, TFSCM, has elapsed.
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 91
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