DSPIC33FJ06GS401-I/ML View Datasheet(PDF) - Microchip Technology
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Description
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DSPIC33FJ06GS401-I/ML Datasheet PDF : 346 Pages
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
FIGURE 6-3:
BROWN-OUT SITUATIONS
VDD
SYSRST
TBOR + TPWRT
VBOR
VDD
SYSRST
VDD
VDD dips before PWRT expires
SYSRST
TBOR + TPWRT
TBOR + TPWRT
VBOR
VBOR
6.3 External Reset (EXTR)
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to Section 24.0 “Electrical Characteristics” for
minimum pulse width specifications. The external
Reset (MCLR) pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.3.0.1 EXTERNAL SUPERVISORY
CIRCUIT
Many systems have external supervisory circuits that
generate Reset signals to reset multiple devices in the
system. This external Reset signal can be directly
connected to the MCLR pin to reset the device when
the rest of system is reset.
6.3.0.2 INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
reset the device, the external Reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
external Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.4 Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
the RESET instruction will remain. SYSRST is released
at the next instruction cycle and the Reset vector fetch
will commence.
The Software Reset (SWR) flag (instruction) in the
Reset Control (RCON<6>) register is set to indicate
the software Reset.
6.5 Watchdog Time-out Reset (WDTO)
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out (WDTO) flag in the
Reset Control (RCON<4>) register is set to indicate
the Watchdog Reset. Refer to Section 21.4
“Watchdog Timer (WDT)” for more information on
Watchdog Reset.
6.6 Trap Conflict Reset
If a lower priority hard trap occurs while a higher
priority trap is being processed, a hard Trap Conflict
Reset occurs. The hard traps include exceptions of pri-
ority level 13 through level 15, inclusive. The address
error (level 13) and oscillator error (level 14) traps fall
into this category.
The Trap Reset (TRAPR) flag in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on Trap Conflict Resets.
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 93
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