DSPIC30F2012AT-20E/ML-ES View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC30F2012AT-20E/ML-ES Datasheet PDF : 206 Pages
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dsPIC30F2011/2012/3012/3013
FIGURE 15-2:
UART RECEIVER BLOCK DIAGRAM
Internal Data Bus
16
Read
Write
Read Read
Write
UxMODE
UxSTA
URX8 UxRXREG Low Byte
Receive Buffer Control
– Generate Flags
– Generate Interrupt
– Shift Data Characters
LPBACK
From UxTX
1
UxRX 0
· Start bit Detect
· Parity Check
· Stop bit Detect
· Shift Clock Generation
· Wake Logic
8-9
Load RSR
to Buffer
Receive Shift Register
(UxRSR)
16 Divider
Control
Signals
16x Baud Clock from
Baud Rate Generator
UxRXIF
DS70139F-page 104
© 2008 Microchip Technology Inc.
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