dsPIC30F2011/2012/3012/3013
FIGURE 1-3:
dsPIC30F3012 BLOCK DIAGRAM
Interrupt
Controller
24
Address Latch
Program Memory
(24 Kbytes)
Data EEPROM
(1 Kbytes)
Data Latch
Y Data Bus
PSV & Table
Data Access
24 Control Block
8
16
24
PCU PCH PCL
Program Counter
Stack
Control
Logic
Loop
Control
Logic
X Data Bus
16 16
16
16
Data Latch
Y Data
RAM
(1 Kbytes)
Address
Latch
Data Latch
X Data
RAM
(1 Kbytes)
Address 16
Latch
16 16
16
Y AGU
X RAGU
X WAGU
Effective Address
PORTB
16
ROM Latch
16
24
16
Instruction
Decode &
Control
IR
Decode
16
16 x 16
W Reg Array
16 16
OSC1/CLKI
Timing
Generation
MCLR
VDD, VSS
AVDD, AVSS
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer
Low-Voltage
Detect
DSP
Engine
Divide
Unit
ALU<16>
16
16
PORTC
PORTD
12-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C™
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4
PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5
AN6/SCK1/INT0/OCFA/RB6
EMUD2/AN7/OC2/IC2/INT2/RB7
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
OSC2/CLKO/RC15
EMUC2/OC1/IC1/INT1/RD0
Timers
SPI1
UART1
DS70139F-page 14
© 2008 Microchip Technology Inc.