DSPIC30F2012AT-20E/ML-ES View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC30F2012AT-20E/ML-ES

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC30F2011/2012/3012/3013

12.0 OUTPUT COMPARE MODULE

Note:

This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

This section describes the output compare module and

associated operational modes. The features provided

by this module are useful in applications requiring

operational modes, such as:

• Generation of Variable Width Output Pulses

• Power Factor Correction

Figure 12-1 depicts a block diagram of the output

compare module.

The key operational features of the output compare

module include:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare During Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

These operating modes are determined by setting the

appropriate bits in the 16-bit OC1CON and OC2CON

registers. The dsPIC30F2011/2012/3012/3013 devices

have 2 compare channels.

OCxRS and OCxR in Figure 12-1 represent the Dual

FIGURE 12-1:

OUTPUT COMPARE MODE BLOCK DIAGRAM

Set Flag bit

OCxIF

OCxRS

OCxR

Comparator

OCTSEL

0

1

0

Output

Logic

3

OCM<2:0>

Mode Select

1

SQ

R

Output OCx

Enable

OCFA

(for x = 1, 2, 3 or 4)

From GP

Timer Module

TMR2<15:0

TMR3<15:0> T2P2_MATCH T3P3_MATCH

Note:

Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channel (1 or 2).

© 2008 Microchip Technology Inc.

DS70139F-page 87

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