DSPIC30F2012AT-20E/ML-ES View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC30F2012AT-20E/ML-ES Datasheet PDF : 206 Pages
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dsPIC30F2011/2012/3012/3013
FIGURE 13-2:
SPI MASTER/SLAVE CONNECTION
SPI Master
Serial Input Buffer
(SPI1BUF)
SDO1
SDI1
SPI Slave
Serial Input Buffer
(SPI1BUF)
Shift Register
(SPI1SR)
MSb
LSb
PROCESSOR 1
SDI1
Serial Clock
SCK1
SDO1
Shift Register
(SPI1SR)
MSb
LSb
SCK1
PROCESSOR 2
13.3 Slave Select Synchronization
The SS1 pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SS1
pin control enabled (SSEN = 1). When the SS1 pin is
low, transmission and reception are enabled and the
SDOx pin is driven. When SS1 pin goes high, the
SDOx pin is no longer driven. Also, the SPI module is
resynchronized, and all counters/control circuitry are
reset. Therefore, when the SS1 pin is asserted low
again, transmission/reception will begin at the MSb
even if SS1 had been de-asserted in the middle of a
transmit/receive.
13.4 SPI Operation During CPU Sleep
Mode
During Sleep mode, the SPI module is shut down. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
13.5 SPI Operation During CPU Idle
Mode
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPI1STAT<13>)
selects if the SPI module will stop or continue on idle. If
SPISIDL = 0, the module will continue to operate when
the CPU enters Idle mode. If SPISIDL = 1, the module
will stop when the CPU enters Idle mode.
© 2008 Microchip Technology Inc.
DS70139F-page 93
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