DSPIC30F2012AT-20E/ML View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC30F2012AT-20E/ML Datasheet PDF : 206 Pages
| |||
dsPIC30F2011/2012/3012/3013
14.0 I2C™ MODULE
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
The Inter-Integrated Circuit (I2CTM) module provides
complete hardware support for both Slave and
Multi-Master modes of the I2C serial communication
standard, with a 16-bit interface.
This module offers the following key features:
• I2C interface supporting both master and slave
operation.
• I2C Slave mode supports 7 and 10-bit address.
• I2C Master mode supports 7 and 10-bit address.
• I2C port allows bidirectional transfers between
master and slaves.
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I2C supports multi-master operation; detects bus
collision and will arbitrate accordingly.
14.1 Operating Function Description
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
Thus, the I2C module can operate either as a slave or
a master on an I2C bus.
FIGURE 14-1:
PROGRAMMER’S MODEL
Bit 15
Bit 15
Bit 7
Bit 7
Bit 8
Bit 9
14.1.1 VARIOUS I2C MODES
The following types of I2C operation are supported:
• I2C slave operation with 7-bit address
• I2C slave operation with 10-bit address
• I2C master operation with 7 or 10-bit address
See the I2C programmer’s model (Figure 14-1).
14.1.2 PIN CONFIGURATION IN I2C MODE
I2C has a 2-pin interface: the SCL pin is clock and the
SDA pin is data.
14.1.3 I2C REGISTERS
I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and
writable. The lower 6 bits of I2CSTAT are read-only.
The remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer as shown in Figure 14-1.
I2CTRN is the transmit register to which bytes are
written during a transmit operation, as shown in
Figure 14-2.
The I2CADD register holds the slave address. A Status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator reload
value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and an interrupt pulse is generated. During
transmission, the I2CTRN is not double-buffered.
Note:
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
I2CRCV (8 bits)
Bit 0
I2CTRN (8 bits)
Bit 0
I2CBRG (9 bits)
Bit 0
I2CCON (16 bits)
Bit 0
I2CSTAT (16 bits)
Bit 0
I2CADD (10 bits)
Bit 0
© 2008 Microchip Technology Inc.
DS70139F-page 95
Share Link: 