ST7PLITEU09M3TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7PLITEU09M3TR Datasheet PDF : 115 Pages
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ST7LITEU05 ST7LITEU09
7.4 REGISTER DESCRIPTION
MULTIPLEXED IO RESET CONTROL REGIS-
TER 1 (MUXCR1)
Read / Write once only
Reset Value: 0000 0000 (00h)
7
0
MIR1 MIR1 MIR1 MIR1 MIR1 MIR1 MIR MIR
5
4
3
2
1
0 98
MULTIPLEXED IO RESET CONTROL REGIS-
TER 0 (MUXCR0)
Read / Write once only
Reset Value: 0000 0000 (00h)
7
0
MIR7 MIR6 MIR5 MIR4 MIR3 MIR2 MIR1 MIR0
Bits 15:0 = MIR[15:0]
This 16-bit register is read/write by software but
can be written only once between two reset
events. It is cleared by hardware after a reset;
When both MUXCR0 and MUXCR1 registers are
at 00h, the multiplexed PA3/RESET pin will act as
RESET. To configure this pin as output (Port A3),
write 55h to MUXCR0 and AAh to MUXCR1.
These registers are one-time writable only.
– To configure PA3 as general purpose output:
After power-on / reset, the application program
has to configure the I/O port by writing to these
registers as described above. Once the pin is
configured as an I/O output, it cannot be
changed back to a reset pin by the application
code.
– To configure PA3 as RESET:
An internally generated reset (such as POR,
LVD, WDG, illegal opcode) will clear the two reg-
isters and the pin will act again as a reset func-
tion. Otherwise, a power-down is required to put
the pin back in reset configuration.
Table 9. Multiplexed IO Register Map and Reset Values
Address
(Hex.)
0047h
0048h
Register
Label
MUXCR0
Reset Value
MUXCR1
Reset Value
7
MIR7
0
MIR15
0
6
MIR6
0
MIR14
0
5
MIR5
0
MIR13
0
4
MIR4
0
MIR12
0
3
MIR3
0
MIR11
0
2
MIR2
0
MIR10
0
1
MIR1
0
MIR9
0
0
MIR0
0
MIR8
0
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