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STM8AF6268TC View Datasheet(PDF) - STMicroelectronics

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STM8AF6268TC Datasheet PDF : 89 Pages
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Interrupt table
8
Interrupt table
STM8AF61xx, STM8AF62xx
Table 16. STM8A interrupt table
Priority
Source
block
Description
Interrupt vector Wakeup
address from Halt
Comments
— Reset
Reset
0x00 6000
— TRAP
SW interrupt
0x00 8004
0 TLI
External top level interrupt 0x00 8008
1 AWU
Auto-wakeup from Halt
0x00 800C
2
Clock
controller
Main clock controller
0x00 8010
3 MISC
Ext interrupt E0
0x00 8014
4 MISC
Ext interrupt E1
0x00 8018
5 MISC
Ext interrupt E2
0x00 801C
6 MISC
Ext interrupt E3
0x00 8020
7 MISC
Ext interrupt E4
8 Reserved(1)
9 Reserved(1)
0x00 8024
10 SPI
End of transfer
0x00 8030
11 Timer 1
Update/overflow/
trigger/break
0x00 8034
12 Timer 1 Capture/compare
0x00 8038
13 Timer 2 Update/overflow
0x00 803C
14 Timer 2 Capture/compare
0x00 8040
15 Timer 3 Update/overflow
0x00 8044
16 Timer 3 Capture/compare
17 Reserved(1)
18 Reserved(1)
19 I2C
I2C interrupts
0x00 8048
0x00 8054
20 LINUART Tx complete/error
0x00 8058
21 LINUART Receive data full reg.
0x00 805C
22 ADC
End of conversion
0x00 8060
23 Timer 4 Update/overflow
0x00 8064
End of Programming/
24 EEPROM
Write in not allowed area
0x00 8068
Yes Reset vector in ROM
Yes
Yes
Port A interrupts
Yes
Port B interrupts
Yes
Port C interrupts
Yes
Port D interrupts
Yes
Port E interrupts
Yes
Yes
1. All reserved and unused interrupts must be initialized with ‘IRET’ for robust programming.
40/89
Doc ID 14952 Rev 6

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