dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-9: DSADR: MOST RECENT DMA RAM ADDRESS
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
DSADR<15:8>
R-0
R-0
bit 8
R-0
bit 7
R-0
R-0
R-0
R-0
R-0
DSADR<7:0>
R-0
R-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 139