DSPIC33FJ64GP202-E/SP View Datasheet(PDF) - Microchip Technology
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DSPIC33FJ64GP202-E/SP Datasheet PDF : 402 Pages
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
9.1.4 PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 9-2.
The output of the primary oscillator or FRC, denoted as
‘FIN’, is divided down by a prescale factor (N1) of 2, 3,
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale factor ‘N1’ is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor
‘N2.’ This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25-40 MIPS.
For a primary oscillator or FRC oscillator, output ‘FIN’,
the PLL output ‘FOSC’ is given by:
EQUATION 9-2: FOSC CALCULATION
( ) FOSC = FIN •
M
N1 • N2
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL.
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
• If PLLPOST<1:0> = 0, then N2 = 2. This provides
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
EQUATION 9-3: XT WITH PLL MODE
EXAMPLE
( ) FOSC 1 10000000 • 32
FCY =
=
= 40 MIPS
22
2•2
FIGURE 9-2:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 PLL BLOCK DIAGRAM
0.8-8.0 MHz
Here(1)
Source (Crystal, External Clock
or Internal RC)
PLLPRE
X
N1
Divide by
2-33
FVCO
100-200 MHz
Here(1)
12.5-80 MHz
Here(1)
VCO
PLLPOST
FOSC
PLLDIV
M
Divide by
2-513
N2
Divide by
2, 4, 8
Note 1: This frequency range must be satisfied at all times.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 143
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