dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
CMPMD RTCCMD
bit 15
R/W-0
PMPMD
bit 8
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
CRCMD DAC1MD
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5-0
Unimplemented: Read as ‘0’
CMPMD: Comparator Module Disable bit
1 = Comparator module is disabled
0 = Comparator module is enabled
RTCCMD: RTCC Module Disable bit
1 = RTCC module is disabled
0 = RTCC module is enabled
PMPMD: PMP Module Disable bit
1 = PMP module is disabled
0 = PMP module is enabled
CRCMD: CRC Module Disable bit
1 = CRC module is disabled
0 = CRC module is enabled
DAC1MD: DAC1 Module Disable bit
1 = DAC1 module is disabled
0 = DAC1 module is enabled
Unimplemented: Read as ‘0’
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 157