dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-15: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
U-0
—
bit 7
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
COFSR<4:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
COFSR<4:0>: Assign DCI Frame Sync Input (COFS) to the corresponding RPn pin
11111 = Input tied to VSS
11001 = Input tied to RP25
•
•
•
00001 = Input tied to RP1
00000 = Input tied to RP0
REGISTER 11-16: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
U-0
—
bit 7
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
C1RXR<4:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
C1RXR<4:0>: Assign ECAN1Receive (C1RX) to the corresponding RPn pin
11111 = Input tied to VSS
11001 = Input tied to RP25
•
•
•
00001 = Input tied to RP1
00000 = Input tied to RP0
Note 1: This register is disabled on devices without ECAN™ module.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 179