DSPIC33FJ32GP302T-I/SO View Datasheet(PDF) - Microchip Technology
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DSPIC33FJ32GP302T-I/SO Datasheet PDF : 402 Pages
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED)
bit 1
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
bit 0
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 31
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