DSPIC33FJ32GP302T-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ32GP302T-I/SO Datasheet PDF : 402 Pages
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
M
Memory Organization.......................................................... 37
Microchip Internet Web Site .............................................. 401
Modes of Operation
Disable ...................................................................... 223
Initialization ............................................................... 223
Listen All Messages .................................................. 223
Listen Only ................................................................ 223
Loopback .................................................................. 223
Normal Operation...................................................... 223
Modulo Addressing ............................................................. 65
Applicability ................................................................. 66
Operation Example ..................................................... 65
Start and End Address................................................ 65
W Address Register Selection .................................... 65
MPLAB ASM30 Assembler, Linker, Librarian ................... 320
MPLAB ICD 3 In-Circuit Debugger System ...................... 321
MPLAB Integrated Development Environment Software .. 319
MPLAB PM3 Device Programmer .................................... 322
MPLAB REAL ICE In-Circuit Emulator System................. 321
MPLINK Object Linker/MPLIB Object Librarian ................ 320
N
NVM Module
Register Map............................................................... 62
O
Open-Drain Configuration ................................................. 160
Output Compare ............................................................... 197
P
Packaging ......................................................................... 379
Details ....................................................................... 380
Marking ..................................................................... 379
Peripheral Module Disable (PMD) .................................... 154
PICkit 2 Development Programmer/Debugger and
PICkit 2 Debug Express............................................ 322
PICkit 3 In-Circuit Debugger/Programmer and
PICkit 3 Debug Express............................................ 321
Pinout I/O Descriptions (table) ............................................ 17
PMD Module
Register Map............................................................... 62
PORTA
Register Map......................................................... 60, 61
PORTB
Register Map............................................................... 61
Power-on Reset (POR) ....................................................... 84
Power-Saving Features .................................................... 153
Clock Frequency and Switching................................ 153
Program Address Space ..................................................... 37
Construction................................................................ 68
Data Access from Program Memory
Using Program Space Visibility........................... 71
Data Access from Program Memory
Using Table Instructions ..................................... 70
Data Access from, Address Generation...................... 69
Memory Map ............................................................... 37
Table Read Instructions
TBLRDH ............................................................. 70
TBLRDL .............................................................. 70
Visibility Operation ...................................................... 71
Program Memory
Interrupt Vector ........................................................... 38
Organization................................................................ 38
Reset Vector ............................................................... 38
R
Reader Response............................................................. 402
Register Map
CRC............................................................................ 60
Dual Comparator ........................................................ 60
Parallel Master/Slave Port .......................................... 59
Real-Time Clock and Calendar .................................. 60
Registers
AD1CHS0 (ADC1 Input Channel 0 Select................ 263
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 262
AD1CON1 (ADC1 Control 1) .................................... 257
AD1CON2 (ADC1 Control 2) .................................... 259
AD1CON3 (ADC1 Control 3) .................................... 260
AD1CON4 (ADC1 Control 4) .................................... 261
AD1CSSL (ADC1 Input Scan Select Low) ............... 264
AD1PCFGL (ADC1 Port Configuration Low) ............ 264
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 233
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 234
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 234
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 235
CiCFG1 (ECAN Baud Rate Configuration 1)............ 231
CiCFG2 (ECAN Baud Rate Configuration 2)............ 232
CiCTRL1 (ECAN Control 1) ...................................... 224
CiCTRL2 (ECAN Control 2) ...................................... 225
CiEC (ECAN Transmit/Receive Error Count) ........... 231
CiFCTRL (ECAN FIFO Control) ............................... 227
CiFEN1 (ECAN Acceptance Filter Enable)............... 233
CiFIFO (ECAN FIFO Status) .................................... 228
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 237,
238
CiINTE (ECAN Interrupt Enable) .............................. 230
CiINTF (ECAN Interrupt Flag) .................................. 229
CiRXFnEID (ECAN Acceptance Filter n
Extended Identifier) .......................................... 237
CiRXFnSID (ECAN Acceptance Filter n
Standard Identifier) ........................................... 236
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 240
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 240
CiRXMnEID (ECAN Acceptance Filter Mask n
Extended Identifier) .......................................... 239
CiRXMnSID (ECAN Acceptance Filter Mask n
Standard Identifier) ........................................... 239
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 241
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 241
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 243,
244, 246
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 242
CiVEC (ECAN Interrupt Code) ................................. 226
CLKDIV (Clock Divisor) ............................................ 147
CORCON (Core Control) ...................................... 30, 93
DCICON1 (DCI Control 1) ........................................ 248
DCICON2 (DCI Control 2) ........................................ 249
DCICON3 (DCI Control 3) ........................................ 250
DCISTAT (DCI Status) ............................................. 251
DMACS0 (DMA Controller Status 0) ........................ 136
DMACS1 (DMA Controller Status 1) ........................ 138
DMAxCNT (DMA Channel x Transfer Count) ........... 135
DMAxCON (DMA Channel x Control)....................... 132
DMAxPAD (DMA Channel x Peripheral Address) .... 135
DMAxREQ (DMA Channel x IRQ Select) ................. 133
DMAxSTA (DMA Channel x RAM Start Address A) . 134
DMAxSTB (DMA Channel x RAM Start Address B) . 134
DSADR (Most Recent DMA RAM Address) ............. 139
I2CxCON (I2Cx Control)........................................... 209
I2CxMSK (I2Cx Slave Mode Address Mask)............ 213
I2CxSTAT (I2Cx Status) ........................................... 211
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 395
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