M38501E5-SP View Datasheet(PDF) - Renesas Electronics
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M38501E5-SP Datasheet PDF : 287 Pages
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APPENDIX
3.7 Machine instructions
Symbol
Function
SBC
(Note 1)
(Note 5)
When T = 0
A
←
A
–
M
–
_
C
When T = 1
M(X)
←
M(X)
–
M
–
_
C
SEB
SEC
Ai or Mi ← 1
C←1
Addressing mode
Details
IMP
IMM
A
BIT, A
ZP
BIT, ZP
OP n # OP n # OP n # OP n # OP n # OP n #
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the con-
tents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
E9 2 2
E5 3 2
This instruction sets the designated bit i of A
or M.
This instruction sets C.
38 2 1
0+B 2 1
20i
0+F 5 2
20i
SED
D←1
This instruction set D.
F8 2 1
SEI
I←1
This instruction set I.
78 2 1
SET
T←1
This instruction set T.
32 2 1
STA
STP
M←A
STX
STY
TAX
TAY
TST
TSX
TXA
M←X
M←Y
X←A
Y←A
M = 0?
X←S
A←X
This instruction stores the contents of A in M.
The contents of A does not change.
This instruction resets the oscillation control F/ 42 2 1
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
This instruction stores the contents of X in M.
The contents of X does not change.
This instruction stores the contents of Y in M.
The contents of Y does not change.
This instruction stores the contents of A in X. AA 2 1
The contents of A does not change.
This instruction stores the contents of A in Y. A8 2 1
The contents of A does not change.
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
This instruction transfers the contents of S in BA 2 1
X.
This instruction stores the contents of X in A. 8A 2 1
85 4 2
86 4 2
84 4 2
64 3 2
TXS
S←X
This instruction stores the contents of X in S. 9A 2 1
TYA
A←Y
This instruction stores the contents of Y in A. 98 2 1
WIT
The WIT instruction stops the internal clock C2 2 1
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All regis-
ters or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
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3850 Group (Spec. H) User’s Manual
APPENDIX
3.7 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
ABS ABS, X ABS, Y
IND ZP, IND IND, X IND, Y
REL
SP 7 6 5 4 3 2 1 0
OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # N V T B D I Z C
F5 4 2
ED 4 3 FD 5 3 F9 5 3
E1 6 2 F1 6 2
NV • • • • ZC
95 5 2
8D 5 3 9D 6 3 99 6 3
96 5 2 8E 5 3
94 5 2
8C 5 3
81 7 2 91 7 2
••••••••
• • • • • • •1
• • • •1• • •
• • • • •1• •
• •1• • • • •
••••••••
••••••••
••••••••
••••••••
N• • • • •Z•
N• • • • •Z•
N• • • • •Z•
N• • • • •Z•
N• • • • •Z•
••••••••
N• • • • •Z•
••••••••
3850 Group (Spec. H) User’s Manual
3-77
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