AD628ARMZ-RL View Datasheet(PDF) - Analog Devices
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AD628ARMZ-RL Datasheet PDF : 20 Pages
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APPLICATIONS
GAIN ADJUSTMENT
The AD628 system gain is provided by an architecture
consisting of two amplifiers. The gain of the input stage
is fixed at 0.1; the output buffer is user-adjustable as
GA2 = 1 + REXT1/REXT2. The system gain is then
GTOTAL
=
0.1× ⎜⎜⎝⎛1 +
R EXT1
REXT2
⎟⎟⎠⎞
(1)
At a 2 nA maximum, the input bias current of the buffer amplifier
is very low and any offset voltage induced at the buffer amplifier
by its bias current may be neglected (2 nA × 10 kΩ = 20 μV).
However, to absolutely minimize bias current effects, select REXT1
and REXT2 so that their parallel combination is 10 kΩ. If practical
resistor values force the parallel combination of REXT1 and REXT2
below 10 kΩ, add a series resistor (REXT3) to make up for the
difference. Table 5 lists several values of gain and corresponding
resistor values.
Table 5. Nearest Standard 1% Resistor Values for
Various Gains1
Total Gain
(V/V)
A2 Gain
(V/V)
REXT1
(Ω)
REXT2
(Ω)
REXT3
(Ω)
0.1
1
10 k
∞
0
0.2
2
20 k
20 k
0
0.25
2.5
25.9 k 18.7 k 0
0.5
5
49.9 k 12.4 k 0
1
10
100 k 11 k
0
2
20
200 k 10.5 k 0
5
50
499 k 10.2 k 0
10
100
1M
10.2 k 0
1 See Figure 29.
To set the system gain to less than 0.1, create an attenuator by
placing Resistor REXT4 from Pin 4 (CFILT) to the reference voltage.
A divider is formed by the 10 kΩ resistor that is in series with
the positive input of A2 and Resistor REXT4. A2 is configured for
unity gain.
Using a divider and setting A2 to unity gain yields
GW / DIVIDER
=
0.1 ×
⎜⎛
⎜⎝ 10
REXT4
kΩ + REXT4
⎟⎞
⎟⎠
×1
AD628
INPUT VOLTAGE RANGE
VREF and the supply voltage determine the common-mode
input voltage range. The relation is expressed by
VCMUPPER ≤ 11(VS+ –1.2 V) − 10 VREF
(2)
VCMLOWER ≥ 11(VS− + 1.2 V) − 10 VREF
where VS+ is the positive supply, VS− is the negative supply,
and 1.2 V is the headroom needed for suitable performance.
Equation 2 provides a general formula for calculating the
common-mode input voltage range. However, keep the AD628
within the maximum limits listed in Table 1 to maintain
optimal performance. This is illustrated in Figure 30 where the
maximum common-mode input voltage is limited to ±120 V.
Figure 31 shows the common-mode input voltage bounds for
single-supply voltages.
200
150
100
50
0
MAXIMUM INPUT COMMON-MODE
VOLTAGE WHEN VREF = GND
–50
–100
–150
–200
0
2
4
6
8
10
12
14
16
SUPPLY VOLTAGE (±V)
Figure 30. Input Common-Mode Voltage vs. Supply Voltage
for Dual Supplies
100
80
60
40
20
0
–20
–40
–60
–80
0
MAXIMUM INPUT COMMON-MODE
VOLTAGE WHEN VREF = MIDSUPPLY
2
4
6
8
10
12
14
16
SINGLE-SUPPLY VOLTAGE (V)
Figure 31. Input Common-Mode Voltage vs.
Supply Voltage for Single Supplies
Rev. F | Page 15 of 20
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