Functional Overview
Table 5: Pin-out 44 Pin, continued
P4[6] I/O
XRES I
P3[0] I/O
P3[2] I/O
P3[4] I/O
P3[6] I/O
P2[0] I/O
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vcc
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I/O
25 Port 4[6]
26 External Reset
27 Port 3[0]
28 Port 3[2]
29 Port 3[4]
30 Port 3[6]
31
Port 2[0] (Non-Multiplexed
Analog Input)
32
Port 2[2] (Non-Multiplexed
Analog Input)
33 Port 2[4] / External AGNDIn
34 Port 2[6] / External VREFIn
35 Port 0[0] (Analog Input)
36 Port 0[2] (Analog Input/Output)
37 Port 0[4] (Analog Input/Output)
38 Port 0[6] (Analog Input)
39 Supply Voltage
40 Port 0[7] (Analog Input)
41 Port 0[5] (Analog Input/Output)
42 Port 0[3] (Analog Input/Output)
43 Port 0[1] (Analog Input)
44 Port 2[7]
P2[5]
P2[3]
P2[1]
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
1 44 43 42 41 40 39 38 37 36 35 34 33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
P2[4]/Ex AGNDIn
P2[2]
P2[0]
P3[6]
P3[4]
P3[2]
P3[0]
Xres
P4[6]
P4[4]
P4[2]
Table 6: Pin-out 48 Pin
Name I/O
P0[7] I/O
P0[5] I/O
P0[3] I/O
P0[1] I/O
P2[7] I/O
P2[5] I/O
P2[3] I/O
P2[1] I/O
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
P4[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
Pin
Description
1 Port 0[7] (Analog Input)
2
Port 0[5] (Analog Input/Out-
put)
3
Port 0[3] (Analog Input/Out-
put)
4 Port 0[1] (Analog Input)
5 Port 2[7]
6 Port 2[5]
7
Port 2[3] (Non-Multiplexed
Analog Input)
8
Port 2[1] (Non-Multiplexed
Analog Input)
9 Port 3[7]
10 Port 3[5]
11 Port 3[3]
12 Port 3[1]
13 Switch Mode Pump
14 Port 4[7]
15 Port 4[5]
16 Port 4[3]
17 Port 4[1]
18 Port 5[3]
19 Port 5[1]
20 Port 1[7]
21 Port 1[5]
22 Port 1[3]
23 Port 1[1] / XtalIn / SCLK
24 Ground
25 Port 1[0] / XtalOut / SDATA
26 Port 1[2]
27 Port 1[4]
28 Port 1[6]
Figure 5: 26643 TQFP
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
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