M38031G9H-XXXSP View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

M38031G9H-XXXSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (Spec.H QzROM version)

Renesas Electronics 

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

• Serial I/O3

Serial I/O3 can be used as either clock synchronous or

asynchronous (UART) serial I/O3. A dedicated timer is also

provided for baud rate generation.

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O3 mode can be selected by setting

the serial I/O3 mode selection bit of the serial I/O3 control

register (bit 6 of address 003216) to “1”.

For clock synchronous serial I/O, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the transmit/receive buffer register.

P34/RXD3

P36/SCLK3

Data bus

Address 003016

Receive buffer register 3

Receive shift register 3

Shift clock

Serial I/O3 control register

Address 003216

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Clock control circuit

f(XIN)

BRG count source selection bit

(f(XCIN) in low-speed mode)

1/4

Serial I/O3 synchronous clock selection bit

Frequency division ratio 1/(n+1)

Baud rate generator 3

1/4

Address 002F16

P37/SRDY3

P35/TXD3

F/F

Falling-edge detector

Clock control circuit

Shift clock

Transmit shift completion flag (TSC)

Transmit shift register 3

Transmit interrupt source selection bit

Transmit interrupt request (TI)

Transmit buffer register 3

Address 003016

Data bus

Transmit buffer empty flag (TBE)

Serial I/O3 status register

Address 003116

Fig 40. Block diagram of clock synchronous serial I/O3

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TXD3

Serial input RXD3

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

Receive enable signal SRDY3

Write pulse to receive/transmit

buffer register (address 003016)

TBE = 0

TBE = 1

TSC = 0

RBF = 1

TSC = 1

Overrun error (OE)

detection

Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit

shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register.

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output

continuously from the TXD pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.

Fig 41. Operation of clock synchronous serial I/O3

Rev.1.10 Nov 14, 2005 Page 50 of 91

REJ03B0166-0110

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