QL7180-6PS484C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
Manufacturer
QL7180-6PS484C Datasheet PDF : 65 Pages
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EclipsePlus Family Data Sheet Rev. A
Pin Descriptions
Table 22: JTAG Pin Descriptions
Pin
Function
TDI/RSI
Test Data In for JTAG/RAM init.
Serial Data In
TRSTB/RRO
Active low Reset for JTAG/RAM
init. reset out
TMS
Test Mode Select for JTAG
TCK
Test Clock for JTAG
TDO/RCO
Test data out for JTAG/RAM init.
clock out
Description
Hold HIGH during normal operation. Connects to serial PROM data
in for RAM initialization. Connect to VCC if unused
Hold LOW during normal operation. Connects to serial PROM reset
for RAM initialization. Connect to GND if unused
Hold HIGH during normal operation. Connect to VCC if not used for
JTAG
Hold HIGH or LOW during normal operation. Connect to VCC or
ground if not used for JTAG
Connect to serial PROM clock for RAM initialization. Must be left
unconnected if not used for JTAG or RAM initialization
NOTE: All JTAG inputs are clamped to the VCC rail, not the VCCIO. Therefore, these pins can only be driven
up to VCC + 0.3 V. These input pins are LVCMOS2 compliant only (2.5 V). All JTAG outputs are driven by the
VCC rail, not VCCIO. Therefore, these output pins can only drive up to VCC + 0.3 V. These output pins are
LVCMOS2 compliant only (2.5 V).
Figure 26: I/O Banks with Relevant Pins
VCCIO (H)
INREF(H)
IOCTRL(H)
IO(H)
VCCIO (G)
INREF(G)
IOCTRL(G)
IO(G)
IO BANK A
IO BANK B
IO BANK F
IO BANK E
VCCIO (C)
INREF(C)
IOCTRL(C)
IO(C)
VCCIO (D)
INREF(D)
IOCTRL(D)
IO(D)
© 2006 QuickLogic Corporation
www.quicklogic.com
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