QL7100-5PS484I View Datasheet(PDF) - QuickLogic Corporation
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QL7100-5PS484I Datasheet PDF : 65 Pages
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EclipsePlus Family Data Sheet Rev. A
Recommended Unused Pin Terminations for the EclipsePlus Devices
All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the
Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the
Placement Editor, choose ConstraintÆFix Placement in the Option pull-down menu of SpDE.
The rest of the pins should be terminated at the board level in the manner presented in Table 24.
Signal Name
PLLOUT<x>a
IOCTRL<y>b
CLK/PLLIN<x>
PLLRST<x>
INREF<y>
Table 24: Recommended Unused Pin Terminations
Recommended Termination
Unused PLL output pins must be connected to either VCC or GND so that their associated input
buffer never floats. Utilized PLL output pins that route the PLL clock outside of the chip should
not be tied to either VCC or GND.
Any unused pins of this type must be connected to either VCC or GND.
Any unused clock pins should be connected to VCC or GND.
If a PLL module is not used, then the associated PLLRST<x> must be connected to VCC; under
normal operation, use it as needed. If PLLs are not used, the associated PLLRST pin must be
connected to the same voltage as VCCPLL (2.5 V or GND).
If an I/O bank does not require the use of INREF signal the pin should be connected to GND.
a. x represents a number.
b. y represents an alphabetical character.
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