QL7100-5PS484I View Datasheet(PDF) - QuickLogic Corporation
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QL7100-5PS484I Datasheet PDF : 65 Pages
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EclipsePlus Family Data Sheet Rev. A
Most QuickLogic products contain four PLLs, one to be used in each quadrant. The PLL presented in
Figure 3 controls the clock tree in the fourth Quadrant of its ESP. As previously mentioned, QuickLogic PLLs
compensate for the additional delay created by the clock tree itself by subtracting the clock tree delay through
the feedback path.
For more specific information on the Phase Locked Loops, please refer to Application Note 58 at
http://www.quicklogic.com/images/appnote58.pdf.
PLL Modes of Operation
QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency—
Table 4 indicates the features of each mode.
PLL Model
PLL_HFb
PLL_LF
PLL_MULT2HF
PLL_MULT2LF
PLL_DIV2HF
PLL_DIV2LF
PLL_MULT4
PLL_DIV4
Table 4: PLL Mode Frequencies
Output Frequency
Input Frequency Rangea
Same as input frequency
66 MHz–150 MHz
Same as input frequency
2 × input frequency
2 × input frequency
1/2 × input frequency
1/2 × input frequency
4 × input frequency
1/4 × input frequency
25 MHz–133 MHz
50 MHz–125 MHz
16 MHz–50 MHz
100 MHz–250 MHz
50 MHz–100 MHz
16 MHz–40 MHz
100 MHz–300 MHz
Output Frequency Range
66 MHz–150 MHz
25 MHz–133 MHz
100 MHz–250 MHz
32 MHz–100 MHz
50 MHz–125 MHz
25 MHz–50 MHz
64 MHz–160 MHz
25 MHz–75 MHz
a. The input frequency can range from 12.5 MHz to 500 MHz, while output frequency ranges from 25 MHz to 250 MHz. When you
add PLLs to your top-level design, be sure that the PLL mode matches your desired input and output frequencies.
b. HF stands for high frequency and LF stands for low frequency.
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