ST62P45BQ1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST62P45BQ1 Datasheet PDF : 72 Pages
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ST62T45B/E45B
4.4 SERIAL PERIPHERAL INTERFACE (SPI)
The on-chip SPI is an optimized serial synchro-
nous interface that supports a wide range of in-
dustry standard SPI specifications. The on-chip
SPI is controlled by small and simple user soft-
ware to perform serial data exchange. The serial
shift clock can be implemented either by software
(using the bit-set and bit-reset instructions), with
the on-chip Timer 1 by externally connecting the
SPI clock pin to the timer pin or by directly apply-
ing an external clock to the Scl line.
The peripheral is composed by an 8-bit Data/shift
Register and a 4-bit binary counter while the Sin
pin is the serial shift input and Sout is the serial
shift output. These two lines can be tied together
to implement two wires protocols (I C-bus, etc).
When data is serialized, the MSB is the first bit.
Sin has to be programmed as input. For serial out-
Figure 25. SPI Block Diagram
put operation Sout has to be programmed as
open-drain output.
The SCL, Sin and Sout SPI clock and data signals
are connected to 3 I/O lines on the same external
pins. With these 3 lines, the SPI can operate in the
following operating modes: Software SPI, S-BUS,
I C-bus and as a standard serial I/O (clock, data,
enable). An interrupt request can be generated af-
ter eight clock pulses. Figure 25 shows the SPI
block diagram.
The SCL line clocks, on the falling edge, the shift
register and the counter. To allow SPI operation in
slave mode, the SCL pin must be programmed as
input and an external clock must be supplied to
this pin to drive the SPI peripheral.
In master mode, SCL is programmed as output, a
clock signal must be generated by software to set
and reset the port line.
SC L
Sin
Sout
CLK
I/O Port
Data Reg
Direction
DIN
I/O Port
Data Reg
Direction
I/O Port
OPR Reg.
0
1 Data Reg
Direction
SPI Interrupt Disable Register
Wr ite
SPI Data Register
Read
RES ET
RESET
Q4
CP
4-Bit Counter
Q4
(Q4=High after Clock8)
DOUT
8-Bit Data
CP
DIN
Shift Register
Reset
Load
DOUT
8-Bit Tristate Data I/O
Output
Enable
D0............... .............D7
to Processor Data Bus
Set Res
Interrupt
VR01504
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