PIC16LF1517T-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LF1517T-I/SO Datasheet PDF : 376 Pages
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TABLE 3-3: PIC16(L)F1516/7 MEMORY MAP (CONTINUED)
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
BANK 13
BANK 14
BANK 15
400h
40Bh
40Ch
46Fh
470h
47Fh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
480h
48Bh
48Ch
4EFh
4F0h
4FFh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
500h
50Bh
50Ch
56Fh
570h
57Fh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
580h
58Bh
58Ch
5EFh
5F0h
5FFh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
600h
60Bh
60Ch
66Fh
670h
67Fh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
680h
68Bh
68Ch
6EFh
6F0h
6FFh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
700h
70Bh
70Ch
76Fh
770h
77Fh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
780h
78Bh
78Ch
7EFh
7F0h
7FFh
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
BANK 16
BANK 17
BANK 18
BANK 19
BANK 20
BANK 21
BANK 22
BANK 23
800h
880h
900h
980h
A00h
A80h
B00h
B80h
Core Registers
Core Registers
Core Registers
Core Registers
Core Registers
Core Registers
Core Registers
Core Registers
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
80Bh
80Ch
86Fh
870h
87Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
88Bh
88Ch
8EFh
8F0h
8FFh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
90Bh
90Ch
96Fh
970h
97Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
98Bh
98Ch
9EFh
9F0h
9FFh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A0Bh
A0Ch
A6Fh
A70h
A7Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A8Bh
A8Ch
AEFh
AF0h
AFFh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
B0Bh
B0Ch
B6Fh
B70h
B7Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
B8Bh
B8Ch
BEFh
BF0h
BFFh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
BANK 24
BANK 25
BANK 26
BANK 27
BANK 28
BANK 29
BANK 30
C00h
C80h
D00h
D80h
E00h
E80h
F00h
Core Registers
Core Registers
Core Registers
Core Registers
Core Registers
Core Registers
Core Registers
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
C0Bh
C0Ch
C6Fh
C70h
C7Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
C8Bh
C8Ch
CEFh
CF0h
CFFh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
D0Bh
D0Ch
D6Fh
D70h
D7Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
D8Bh
D8Ch
DEFh
DF0h
DFFh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
E0Bh
E0Ch
E6Fh
E70h
E7Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
E8Bh
E8Ch
EEFh
EF0h
EFFh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
F0Bh
F0Ch
F6Fh
F70h
F7Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
Legend:
= Unimplemented data memory locations, read as ‘0’.
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