PIC16LF1517T-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LF1517T-I/SO Datasheet PDF : 376 Pages
| |||
PIC16(L)F1516/7/8/9
REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
U-0
U-0
U-0
R/W-0/0
U-0
U-0
OSFIF
—
—
—
BCLIF
—
—
bit 7
R/W-0/0
CCP2IF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-4
bit 3
bit 2-1
bit 0
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF
INTF
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA
PS<2:0>
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE
PIE2
OSFIE
—
—
—
BCLIE
—
—
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF
PIR2
OSFIF
—
—
—
BCLIF
—
—
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.
Bit 0
IOCIF
TMR1IE
CCP2IE
TMR1IF
CCP2IF
Register
on Page
76
151
77
78
79
80
DS41452C-page 80
2010-2012 Microchip Technology Inc.
Share Link: 