PIC16(L)F1516/7/8/9
8.3 Register Definitions: Voltage Regulator Control
REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0
—
bit 7
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
VREGPM
R/W-1/1
Reserved
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
bit 0
Unimplemented: Read as ‘0’
VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC16F1516/7/8/9 only.
2: See Section 25.0 “Electrical Specifications”.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF
INTF
IOCBF
IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1
IOCBN
IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1
IOCBP
IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE
PIE2
OSFIE
—
—
—
BCLIE
—
—
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF
PIR2
OSFIF
—
—
—
BCLIF
—
—
STATUS
—
—
—
TO
PD
Z
DC
VREGCON(1)
—
—
—
—
—
—
VREGPM
WDTCON
—
—
WDTPS<4:0>
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.
Note 1: PIC16F1516/7/8/9 only.
IOCIF
IOCBF0
IOCBN0
IOCBP0
TMR1IE
CCP2IE
TMR1IF
CCP2IF
C
Reserved
SWDTEN
Register
on Page
76
129
129
129
77
78
79
80
21
84
89
DS41452C-page 84
2010-2012 Microchip Technology Inc.