ST72334J4TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72334J4TC

8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces

STMicroelectronics 

ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto

15.9 CONTROL PIN CHARACTERISTICS

15.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ 1)

Max

VIL

Input low level voltage 2)

VIH

Input high level voltage 2)

Vhys Schmitt trigger voltage hysteresis 3)

0.7xVDD

400

0.3xVDD

VOL

Output low level voltage 4)

(see Figure 91, Figure 92)

VDD=5V

IIO=+5mA

IIO=+2mA

0.68

0.95

0.28

0.45

RON Weak pull-up equivalent resistor 5)

VIN=VSS

VDD=5V

VDD=3.4V

20

80

40

100

60

120

tw(RSTL)out Generated reset pulse duration

External pin or

internal reset sources

6

30

th(RSTL)in External reset pulse hold time 6)

tg(RSTL)in Filtered glitch duration 7)

20

100

Unit

V

mV

V

kΩ

1/fSFOSC

µs

µs

ns

Figure 89. Typical Application with RESET Pin 8)

OPTIONAL

USER

EXTERNAL

RESET

CIRCUIT 8)

VDD

VDD

0.1µF 4.7kΩ

0.1µF

VDD

RON

RESET

ST72XXX

INTERNAL

RESET CONTROL

WATCHDOG RESET

LVD RESET

Notes:

1. Unless otherwise specified, typical data is based on TA=25°C and VDD=5V.

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The IIO current sunk must always respect the absolute maximum rating specified in Section 15.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-

scribed in Figure 90). This data is based on characterization results, not tested in production.

6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy

environments.

8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

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