ST72324BLJ2B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72324BLJ2B5

3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface

STMicroelectronics 

ST72324Lxx

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT

low power mode. On the contrary, only external

and other specified interrupts allow the processor

to exit from the HALT modes (see column “Exit

from HALT” in “Interrupt Mapping” table). When

several pending interrupts are present while exit-

ing HALT mode, the first one serviced can only be

an interrupt with exit from HALT mode capability

and it is selected through the same decision proc-

ess shown in Figure 15.

Note: If an interrupt, that is not able to Exit from

HALT mode, is pending with the highest priority

when exiting HALT mode, this interrupt is serviced

after the first one serviced.

Figure 16. Concurrent Interrupt Management

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 16 and Figure 17 show two

different interrupt management modes. The first is

called concurrent mode and does not allow an in-

terrupt to be interrupted, unlike the nested mode in

Figure 17. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,

IT4, IT3, IT2, IT1, IT0. The software priority is giv-

en for each interrupt.

Warning: A stack overflow may occur without no-

tifying the software of the failure.

SOFTWARE

PRIORITY

I1

I0

LEVEL

TRAP

IT0

IT1

IT1

IT2

IT3

RIM

IT4

MAIN

11 / 10

MAIN

10

3

11

3

11

3

11

3

11

3

11

3

11

3/0

Figure 17. Nested Interrupt Management

IT1

IT2

TRAP

IT0

RIM

MAIN

11 / 10

IT4

IT4

IT1

IT3

SOFTWARE

PRIORITY

I1

I0

LEVEL

IT2

MAIN

10

3

11

3

11

2

00

1

01

3

11

3

11

3/0

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