CLC1002ISO8X View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

CLC1002ISO8X

Ultra-Low Noise Amplifer

Exar Corporation 

Data Sheet

Input

+

-

Rf

Rg

Rs

Output

CL

RL

Figure 5. Addition of RS for Driving Capacitive Loads

Table 1 provides the recommended RS for various

capacitive loads. The recommended RS values result in

<=1dB peaking in the frequency response. The Frequency

Response vs. CL plots, on page 7, illustrates the response

of the CLC1002.

CL (pF)

RS (Ω)

-3dB BW (MHz)

3

6

G=5

2

4

1

Output

2

0

0

Input

-1

-2

-2

-4

-3

0

-6

50 100 150 200 250 300 350 400 450

Time (us)

Figure 6. Overdrive Recovery

10

43

275

22

30

235

47

20

190

100

12

146

470

4.3

72

Table 1: Recommended RS vs. CL

For a given load capacitance, adjust RS to optimize the

tradeoff between settling time and bandwidth. In general,

reducing RS will increase bandwidth at the expense of

additional overshoot and ringing.

Overdrive Recovery

An overdrive condition is defined as the point when either

one of the inputs or the output exceed their specified

voltage range. Overdrive recovery is the time needed for

the amplifier to return to its normal or linear operating

point. The recovery time varies, based on whether the

input or output is overdriven and by how much the range

is exceeded. The CLC1002 will typically recover in less

than 25ns from an overdrive condition. Figure 6 shows the

CLC1002 in an overdriven condition.

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. Exar has evaluation boards

to use as a guide for high frequency layout and as aid in

device testing and characterization. Follow the steps below

as a basis for high frequency layout:

▪▪Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

▪▪Place the 6.8µF capacitor within 0.75 inches of the power pin

▪▪Place the 0.1µF capacitor within 0.1 inches of the power pin

▪▪Remove the ground plane under and around the part,

especially near the input and output pins to reduce

parasitic capacitance

▪▪Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more

information.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

Products

CEB002

CLC1002 in SOT23-5

CEB003

CLC1002 in SOIC-8

©2007-2013 Exar Corporation

15/17

Rev 1G

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