QL8325-8PV100M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL8325-8PV100M

Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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Vpump

Vded

VccPLL

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Charge Pump Disable

This pin disables the internal charge pump for lower static power

operation. To disable the charge pump, connect Vpump to 3.3 V.

If the Disable Charge Pump feature is not used, connect Vpump to

Ground. For backwards compatibility with Eclipse and EclipsePlus

devices, connect Vpump to Ground.

Voltage tolerance for clocks,

JTAG, and IOCTRL/Voltage

Drive for PLLOUT and JTAG

pins

This pin specifies the input voltage tolerance for CLK, JTAG, and

IOCTRL dedicated input pins, as well as the output voltage drive

for PLLOUT and JTAG pins. If the PLLs are used, Vded must be

the same as VCCPLL. For backwards compatibility with Eclipse and

EclipsePlus devices, connect Vded to 2.5 V.

Power Supply pin for PLL

Connect to 2.5 V supply or 3.3 V supply. For backwards

compatibility with Eclipse and EclipsePlus devices, connect to

2.5 V.

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